In the midst of a media campaign that has teased the market with hints
of breakthrough performance and expanded parallelism, several insiders
are now referring to the forthcoming architecture as Intel Corp.'s
Scott Emmo, Hewlett-Packard technology manager for the Advanced Technology
Marketing Group in Palo Alto, CA, concedes that Intel (with whom HP
developed Merced's EPIC architecture), has cloaked the project in
a veil of secrecy that may have backfired by generating more speculation
than either company anticipated.
"I think the reason why there's been so many rumors about Merced and
the architecture is that it was filling a void of information, because
Intel and HP really haven't said a whole lot about it in the past,
" he says. "People are guessing. Understand that Merced is a couple
of years off - in general, that kind of information isn't usually
brought out anyway."
Key to the hype surrounding Merced is EPIC (Explicitly Parallel Instruction
Computing). While most of today's 32-bit chips allow processors to
execute four tasks at once - or in parallel - EPIC would expand parallelism
without taking up more room on the microprocessor. That's because
EPIC takes the complexity of parallelism out of the processor and
allows the compiler to perform those tasks outside of the hardware.
Apart from pumping up clock speeds, Emmo says EPIC is the only other
way the industry will see more performance out of a chip.
"The analogy would be, if I've got a one-lane highway, cranking up
the clock speed would be like raising the speed limit," he says. "
I could get a lot more cars down the highway, but I'd have to go from
60 miles an hour to 80 miles an hour. In parallel, it's widening the
lanes. Today they only have four lanes, so I can get quite a few cars
down there, but by combining the two of them, I can get super performance
and I'm able to increase my lanes much easier."
The question is, who needs it? Bruce Lightner, vice-president of development
at Metaflow Technologies in La Jolla, CA, says the whole idea may
be premature, as much of the market has yet to make the transition
from 16- to 32-bit architecture. He also doubts any of the new chip
series will be seen before 1999, which has been the date reported
for Merced's debut.
"This is going to take a lot longer than any of us can imagine," he
says. "Intel has been trying to defocus on x86 performance. They really
made a big blunder with the Pentium Pro when they ignored 16-bit performance,
and part of this may be that Microsoft told them all that stuff is
going to be gone by (the year 2000). That idea has persisted, and
certainly if you've ever taken a 16-bit application and run it on
a Pentium Pro, it's horrible. I think Intel is seeing that x86 performance
is still very important, which has been another reason for putting
"After they've floated this trial balloon, I'm certainly picking up
the signs that they're re-trenching in the x86, making the Pentium
product line a better thing. That's not something they were saying
just before their Merced announcement."
Intel spokesperson Chuck Mulloy says the company's investment in Merced
doesn't mean abandoning other product lines.
"The Merced product line is over and above and beyond 32-bit processors,
and it doesn't mean we'll stop 32-bit architecture processors," he
says. "Merced will come in initially at the high end of the service
space, and maybe over time into high-end workstations, but we don'
t think people have fully utilized the capabilities of 32-bit (either).
We'll continue to push both."
While HP worked with Intel on the architecture, they'll have to buy
it from the chip giant, just like any other vendor. That's fine with
Emmo, who says the open-market approach will make Merced a standard.
But Lightner points out that fabrication is a very expensive part
of the business, which may explain HP's laissez-faire attitude to
COPYRIGHT 1998 Plesman Publications Ltd. (Canada)
Schick, Shane, Merced could be Intel's 'trial balloon.' (next generation processor)., Vol. 14, Computer Dealer News, 01-19-1998, pp 10(1).